diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-24 13:06:12 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:13:26 +0200 |
| commit | 9506aea3511d626da936df0cee431b6dcabb8734 (patch) | |
| tree | a41385b9ee305c60a0f5b6cfabf04d176d6e0970 /src/mainboard/google/glados/spd | |
| parent | ffdf901c765db8bb01006fa81839fb5703eea4e1 (diff) | |
glados: move to native gpio configuration
Instead of relying on FSP to do gpio configuration in one
place use the native support in coreboot. This also removes
the open coded configuration of the memory configuration
ids.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289800
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11175
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/glados/spd')
| -rw-r--r-- | src/mainboard/google/glados/spd/spd.c | 45 |
1 files changed, 9 insertions, 36 deletions
diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 1882fa7494..d5d96b6ead 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -21,10 +21,9 @@ #include <arch/byteorder.h> #include <cbfs.h> #include <console/console.h> +#include <gpio.h> #include <string.h> -#include <soc/gpio.h> #include <soc/pei_data.h> -#include <soc/pcr.h> #include <soc/romstage.h> #include "spd.h" @@ -85,42 +84,16 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) char *spd_file; size_t spd_file_len; int spd_index; - int spd_gpio[4]; - - /************************************************************* - * FIXME: Remove when real GPIO support is ready. - */ - GPIO_PAD gpio_set[4] = { - GPIO_LP_GPP_C12, /* PCH_MEM_CONFIG[0] */ - GPIO_LP_GPP_C13, /* PCH_MEM_CONFIG[1] */ - GPIO_LP_GPP_C14, /* PCH_MEM_CONFIG[2] */ - GPIO_LP_GPP_C15, /* PCH_MEM_CONFIG[3] */ - }; - int index; - - for (index = 0; index < ARRAY_SIZE(gpio_set); index++) { - u32 number = GPIO_GET_PAD_NUMBER(gpio_set[index]); - u32 cfgreg = 8 * number + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET; - /* - * Set GPIO mode and enable input - * Clear PMODE0 | PMODE1 | GPIORXDIS - */ - u32 dw0mask = (1 << 10) | (1 << 11) | (1 << 9); - u32 dw0reg = 0; - pcr_andthenor32(PID_GPIOCOM1, cfgreg, ~dw0mask, dw0reg); - - /* Read current input value */ - pcr_read32(PID_GPIOCOM1, cfgreg, &dw0reg); - spd_gpio[index] = !!(dw0reg & (1 << 1)); - } - /*************************************************************/ - spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | - (spd_gpio[1] << 1) | spd_gpio[0]; + gpio_t spd_gpios[] = { + GPP_C12, /* PCH_MEM_CONFIG[0] */ + GPP_C13, /* PCH_MEM_CONFIG[1] */ + GPP_C14, /* PCH_MEM_CONFIG[2] */ + GPP_C15, /* PCH_MEM_CONFIG[3] */ + }; - printk(BIOS_DEBUG, - "SPD: index %d (GPP_C15=%d GPP_C14=%d GPP_C13=%d GPP_C12=%d)\n", - spd_index, spd_gpio[3], spd_gpio[2], spd_gpio[1], spd_gpio[0]); + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + printk(BIOS_ERR, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |