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author | Matt DeVillier <matt.devillier@gmail.com> | 2018-06-26 13:07:32 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-07-21 00:49:25 +0000 |
commit | 0b9cfe60b20b91fc172e041d192e48f4548572f5 (patch) | |
tree | 281c66387dfc7d883a8d97bdd33a3b86c8112194 /src/mainboard/google/glados/romstage.c | |
parent | 86669939ea80d8c90e6fb2676f2fb524005b565b (diff) |
google/glados: Convert to variant setup
Convert Skylake reference board glados to variant setup in
preparation for merge with existing Skylake boards chell and lars,
and upstreaming of new boards asuka, caroline, cave, and sentry.
The following changes have been made:
- move DPTF to variant subdir
- move non-common EC defs to variant subdir
- adjust Kconfig for variant setup
- move non-common NHLT config to variant Kconfig
- make non-common NHLT ACPI code conditional
- move devicetree to variant subdir
- move board GPIO defs to variant subdir
- move board PEI data to variant subdir
- move SPD index calculation to romstage so available for
dual-channel determination during PEI for boards which need it
- move SPD compilation to variant makefile
- add weak function for determination of dual-channel RAM
- add weak function for mainboard_gpio_smi_sleep() so SKL-Y variants
can override and power down rails as needed
Test: build google/glados
Change-Id: I41615979dc11b5a10e32d6b5f477a256735cde53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/glados/romstage.c')
-rw-r--r-- | src/mainboard/google/glados/romstage.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 72f15f99c3..07f0ff0aca 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -17,13 +17,24 @@ #include <string.h> #include <ec/google/chromeec/ec.h> +#include <gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> #include "spd/spd.h" +#include <variant/gpio.h> void mainboard_romstage_entry(struct romstage_params *params) { + /* Get SPD index */ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + params->pei_data->mem_cfg_id = + gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); |