diff options
| author | Archana Patni <archana.patni@intel.com> | 2015-11-11 01:30:41 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-18 04:42:51 +0100 |
| commit | 30f53cd3973886fb69a59479231656846e11e5ca (patch) | |
| tree | 944f582761c8cd44943512e1d78dfb76cd0971e0 /src/mainboard/google/glados/devicetree.cb | |
| parent | c4511e2b733c2ad37e79de8fed6f786bae0a29e0 (diff) | |
skylake boards: csme: add p2sb device and hecienabled devicetree variable
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0
(default) disables Heci1 and hides the device from OS. It internally uses
the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb
device in the devicetree which is necessary for hiding and unhiding the
device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu.
CQ-DEPEND=CL:*238451
Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05
Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311913
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/glados/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index f6aaac36f0..5356cc1952 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -42,6 +42,7 @@ chip soc/intel/skylake register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" + register "HeciEnabled" = "0" # Enable Root port 1. register "PcieRpEnable[0]" = "1" @@ -126,6 +127,7 @@ chip soc/intel/skylake device pnp 0c09.0 on end end end # LPC Interface + device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus |