google/glados: Convert to variant setup

Convert Skylake reference board glados to variant setup in
preparation for merge with existing Skylake boards chell and lars,
and upstreaming of new boards asuka, caroline, cave, and sentry.

The following changes have been made:
- move DPTF to variant subdir
- move non-common EC defs to variant subdir
- adjust Kconfig for variant setup
- move non-common NHLT config to variant Kconfig
- make non-common NHLT ACPI code conditional
- move devicetree to variant subdir
- move board GPIO defs to variant subdir
- move board PEI data to variant subdir
- move SPD index calculation to romstage so available for
    dual-channel determination during PEI for boards which need it
- move SPD compilation to variant makefile
- add weak function for determination of dual-channel RAM
- add weak function for mainboard_gpio_smi_sleep() so SKL-Y variants
    can override and power down rails as needed

Test: build google/glados

Change-Id: I41615979dc11b5a10e32d6b5f477a256735cde53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 3 insertions, 72 deletions

diff --git a/src/mainboard/google/glados/acpi/dptf.asl b/src/mainboard/google/glados/acpi/dptf.asl
index 8e963155fd..0af7e9b94a 100644
--- a/src/mainboard/google/glados/acpi/dptf.asl
+++ b/src/mainboard/google/glados/acpi/dptf.asl
@@ -14,77 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#define DPTF_CPU_PASSIVE        80
-#define DPTF_CPU_CRITICAL       90
-#define DPTF_CPU_ACTIVE_AC0     90
-#define DPTF_CPU_ACTIVE_AC1     80
-#define DPTF_CPU_ACTIVE_AC2     70
-#define DPTF_CPU_ACTIVE_AC3     60
-#define DPTF_CPU_ACTIVE_AC4     50
+/* Include Variant DPTF */
+#include <variant/acpi/dptf.asl>
 
-#define DPTF_TSR0_SENSOR_ID	1
-#define DPTF_TSR0_SENSOR_NAME	"Ambient"
-#define DPTF_TSR0_PASSIVE	55
-#define DPTF_TSR0_CRITICAL	70
-
-#define DPTF_TSR1_SENSOR_ID	2
-#define DPTF_TSR1_SENSOR_NAME	"Charger"
-#define DPTF_TSR1_PASSIVE	55
-#define DPTF_TSR1_CRITICAL	70
-
-#define DPTF_TSR2_SENSOR_ID	3
-#define DPTF_TSR2_SENSOR_NAME	"DRAM"
-#define DPTF_TSR2_PASSIVE	55
-#define DPTF_TSR2_CRITICAL	70
-
-#define DPTF_TSR3_SENSOR_ID	4
-#define DPTF_TSR3_SENSOR_NAME	"WiFi"
-#define DPTF_TSR3_PASSIVE	55
-#define DPTF_TSR3_CRITICAL	70
-
-/* SKL-Y EC already has a custom charge profile based on temperature. */
-#undef DPTF_ENABLE_CHARGER
-
-/* SKL-Y is Fanless design. */
-#undef DPTF_ENABLE_FAN_CONTROL
-
-Name (DTRT, Package () {
-	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 0 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 1 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 2 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 3 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
-	0x2,		/* Revision */
-	Package () {	/* Power Limit 1 */
-		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		1600,	/* PowerLimitMinimum */
-		6000,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		200	/* StepSize */
-	},
-	Package () {	/* Power Limit 2 */
-		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		8000,	/* PowerLimitMinimum */
-		8000,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		1000	/* StepSize */
-	}
-})
-
-/* Include DPTF */
+/* Include SoC DPTF */
 #include <soc/intel/skylake/acpi/dptf/dptf.asl>