soc/qualcomm/ipq40xx: Add support for BLSP QUP I2C

Able to talk to the TPM device and the commands
seem to succeed.

BUG=chrome-os-partner:49249 chrome-os-partner:49250
TEST=All commands to the TPM succeed
BRANCH=none

Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd
Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333314
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

squashed:

soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI

- Enable BLSP SPI driver for ipq40xx
- supports only FIFO mode

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9
Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333303
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 77 insertions, 0 deletions

diff --git a/src/mainboard/google/gale/blsp.c b/src/mainboard/google/gale/blsp.c
new file mode 100644
index 0000000000..3be075f141
--- /dev/null
+++ b/src/mainboard/google/gale/blsp.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the depthcharge project.
+ *
+ * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/blsp.h>
+#include <soc/qup.h>
+
+#define IPQ40XX_I2C0_PINGROUP_1		1
+#define IPQ40XX_I2C0_PINGROUP_2		(!IPQ40XX_I2C0_PINGROUP_1)
+
+#if IPQ40XX_I2C0_PINGROUP_1
+
+#define SCL_GPIO		20
+#define SDA_GPIO		21
+#define GPIO_FUNC_SCL		0x1
+#define GPIO_FUNC_SDA		0x1
+
+#elif IPQ40XX_I2C0_PINGROUP_2
+
+#define SCL_GPIO		58
+#define SDA_GPIO		59
+#define GPIO_FUNC_SCL		0x3
+#define GPIO_FUNC_SDA		0x2
+
+#else
+
+#warning "TPM: I2C pingroup not specified"
+
+#endif
+
+int blsp_i2c_init_board(blsp_qup_id_t id)
+{
+	switch (id) {
+	case BLSP_QUP_ID_0:
+	case BLSP_QUP_ID_1:
+	case BLSP_QUP_ID_2:
+	case BLSP_QUP_ID_3:
+#if defined(IPQ40XX_I2C0_PINGROUP_1) || defined(IPQ40XX_I2C0_PINGROUP_2)
+		gpio_tlmm_config_set(SDA_GPIO, GPIO_FUNC_SDA,
+				     GPIO_NO_PULL, GPIO_2MA, 1);
+		gpio_tlmm_config_set(SCL_GPIO, GPIO_FUNC_SCL,
+				     GPIO_NO_PULL, GPIO_2MA, 1);
+#endif /* Pin Group 1 or 2 */
+		break;
+	default:
+		return 1;
+	}
+
+	return 0;
+}