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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-10-23 12:07:58 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-20 17:38:23 +0000 |
| commit | e5b8a04f846874d3282923bf1bf15a2077bd440e (patch) | |
| tree | 094c257629ead4d1b298076aad6406a878fd16f3 /src/mainboard/google/foster/chromeos.c | |
| parent | 1864f12fdaa62a042341180d7438e2b5daaa0904 (diff) | |
mainboard/msi/ms7d25: Configure NCT6687D pin for PECI
One register configuring multi-pin functions was outside of the Global
Configuration Registers space and skipped in the initial port patches.
Replicate the vendor configuration and set the Super I/O pin for PECI
functionality.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/foster/chromeos.c')
0 files changed, 0 insertions, 0 deletions