diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-10 01:24:11 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:13:23 +0000 |
| commit | 97c5464443306f26b61cec3a0f50108a5c06b7ef (patch) | |
| tree | f085457907ad200a0d9d9be8a07c937e755fae91 /src/mainboard/google/fizz | |
| parent | 19c2ce7639d55908d210782ae5a0315396cc7eaf (diff) | |
skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/fizz')
| -rw-r--r-- | src/mainboard/google/fizz/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/variants/karma/overridetree.cb | 4 |
3 files changed, 12 insertions, 5 deletions
diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6627c47481..c86be82c68 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -9,6 +9,7 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <intelblocks/power_limit.h> #include <variant/gpio.h> #include <smbios.h> #include <soc/gpio.h> @@ -99,7 +100,7 @@ static uint8_t board_sku_id(void) * | n (U22) | 29 | .9n | .9n | x(43) | * +-------------+-----+---------+---------+-------+ */ -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -215,9 +216,11 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { + struct soc_power_limits_config *soc_conf; config_t *conf = config_of_soc(); - mainboard_set_power_limits(conf); + soc_conf = &conf->power_limits_config; + mainboard_set_power_limits(soc_conf); dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index f02accec71..b8455fe9e9 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -325,8 +325,10 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "tdp_psyspl2" = "90" - register "psys_pmax" = "120" + register "power_limits_config" = "{ + .tdp_psyspl2 = 90, + .psys_pmax = 120, + }" register "tcc_offset" = "6" # TCC of 94C device cpu_cluster 0 on diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index f978240323..bfa260e9e9 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -17,7 +17,9 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader - register "psys_pmax" = "151" + register "power_limits_config" = "{ + .psys_pmax = 151, + }" device domain 0 on device pci 14.0 on |