diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 00:25:18 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:43:56 +0000 |
| commit | 6c83a71b0a803c922b02b613e927d4c49b944c32 (patch) | |
| tree | 176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/google/fizz | |
| parent | c7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff) | |
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/google/fizz')
3 files changed, 57 insertions, 47 deletions
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index d64a9f9102..a6ec6b62f8 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -233,22 +233,6 @@ chip soc/intel/skylake # RP 12 uses CLK SRC 2 register "PcieRpClkSrcNumber[11]" = "2" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug @@ -306,6 +290,25 @@ chip soc/intel/skylake device ref igpu on end device ref sa_thermal on end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C + [1] = USB2_PORT_MID(OC3), // Type-A Rear + [2] = USB2_PORT_MID(OC2), // Type-A Front + [3] = USB2_PORT_MID(OC2), // Type-A Front + [4] = USB2_PORT_MID(OC1), // Type-A Rear + [5] = USB2_PORT_MID(OC1), // Type-A Rear + [6] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [7] = USB2_PORT_MID(OC_SKIP), // Type-A 2.0 / Debug + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C + [1] = USB3_PORT_DEFAULT(OC3), // Type-A Rear + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Front + [3] = USB3_PORT_DEFAULT(OC2), // Type-A Front + [4] = USB3_PORT_DEFAULT(OC1), // Type-A Rear + [5] = USB3_PORT_DEFAULT(OC1), // Type-A Rear + }" chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 989b2406fb..3da4f0e4f6 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -42,20 +42,6 @@ chip soc/intel/skylake register "PcieRpEnable[10]" = "0" register "PcieRpEnable[11]" = "0" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Rear - register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # None @@ -78,6 +64,23 @@ chip soc/intel/skylake device domain 0 on device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC_SKIP), // Type-C + [1] = USB2_PORT_MID(OC_SKIP), // HDMI + [2] = USB2_PORT_MID(OC2), // Type-A Rear + [3] = USB2_PORT_MID(OC2), // Type-A Rear + [4] = USB2_PORT_MID(OC3), // Type-A Rear + [5] = USB2_PORT_MID(OC_SKIP), // HDMI Audio + [6] = USB2_PORT_MID(OC_SKIP), // Bluetooth + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C + [1] = USB3_PORT_DEFAULT(OC_SKIP), // HDMI + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Rear + [3] = USB3_PORT_DEFAULT(OC2), // Type-A Rear + [4] = USB3_PORT_DEFAULT(OC3), // Type-A Rear + }" chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index d1dc46f45a..25b39f4fbe 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -1,28 +1,32 @@ chip soc/intel/skylake - # Mapping of USB port # to device - #+----------------+-------+-----------------------------------+ - #| Device | Port# | Rev | - #+----------------+-------+-----------------------------------+ - #| USB A Side | 3 | 2/3 | - #| SD Card | 4 | | - #| Camera | 8 | | - #| Touchsreen | 10 | | - #+----------------+-------+-----------------------------------+ - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Side - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen - - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader - register "power_limits_config" = "{ .psys_pmax = 151, }" device domain 0 on device ref south_xhci on + # Mapping of USB port # to device + #+----------------+-------+-----------------------------------+ + #| Device | Port# | Rev | + #+----------------+-------+-----------------------------------+ + #| USB A Side | 3 | 2/3 | + #| SD Card | 4 | | + #| Camera | 8 | | + #| Touchsreen | 10 | | + #+----------------+-------+-----------------------------------+ + register "usb2_ports" = "{ + [2] = USB2_PORT_MID(OC2), // Type-A Side + [3] = USB2_PORT_MID(OC_SKIP), // Card reader + [7] = USB2_PORT_MID(OC_SKIP), // Camera + [9] = USB2_PORT_MID(OC_SKIP), // Touchscreen + }" + + register "usb3_ports" = "{ + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Side + [3] = USB3_PORT_DEFAULT(OC_SKIP), // Card reader + }" + chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi |