diff options
| author | Alexander Goncharov <chat@joursoir.net> | 2023-02-04 15:20:37 +0400 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-02-07 04:37:31 +0000 |
| commit | 893c3ae892961facc9be8bd300160222e694ab34 (patch) | |
| tree | ec628a8f9371fe96b783c7bf11dee59d065c0df5 /src/mainboard/google/fizz | |
| parent | db4b71ff10b48624a1a0b76e3255bd206ef921d5 (diff) | |
tree: Drop repeated words
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fizz')
| -rw-r--r-- | src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 10 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/variants/endeavour/overridetree.cb | 6 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 95d5368f52..74c601a58f 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -168,7 +168,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[2]" = "1" # RP 3, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses uses CLK SRC 0 + # RP 3 uses CLK SRC 0 register "PcieRpClkSrcNumber[2]" = "0" # Enable Root port 4(x1) for WLAN. @@ -181,7 +181,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[3]" = "1" # RP 4, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses uses CLK SRC 5 + # RP 4 uses CLK SRC 5 register "PcieRpClkSrcNumber[3]" = "5" # Enable Root port 5(x4) for NVMe. @@ -207,7 +207,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # Enable Root port 11 for BtoB. @@ -220,7 +220,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[10]" = "1" # RP 11, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses uses CLK SRC 2 + # RP 11 uses CLK SRC 2 register "PcieRpClkSrcNumber[10]" = "2" # Enable Root port 12 for BtoB. @@ -233,7 +233,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[11]" = "1" # RP 12, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses uses CLK SRC 2 + # RP 12 uses CLK SRC 2 register "PcieRpClkSrcNumber[11]" = "2" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 3ca1648e0f..07ed7bcae4 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[6]" = "1" # RP 7, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[6]" = "1" - # RP 7 uses uses CLK SRC 4 + # RP 7 uses CLK SRC 4 register "PcieRpClkSrcNumber[6]" = "4" # Enable Root port 8(x1) for TPU0 @@ -23,7 +23,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[7]" = "1" # RP 8, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[7]" = "1" - # RP 8 uses uses CLK SRC 2 + # RP 8 uses CLK SRC 2 register "PcieRpClkSrcNumber[7]" = "2" # Enable Root port 9(x4) for i350 LAN @@ -34,7 +34,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # These are part of Root port 9(x4) |