diff options
| author | praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2017-12-09 00:51:21 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-13 02:19:54 +0000 |
| commit | d6dffdc1faa4ba97bd5d592997eb32d25ba54f7a (patch) | |
| tree | 3f6fc89dff19d19b59b8a8104fbb268895ee31c9 /src/mainboard/google/fizz | |
| parent | ac9d6b8c739939c45400a55c60f2104ba4eb5e5a (diff) | |
soc/intel/skylake: Enable LPC IO Decoding on PCR
According to the PCH BIOS Spec (Doc#549921/Rev-2.3.4),
section 2.5.1.6, it is a requirement to program the same
value programmed in LPC "PCI offset 82h" into "PCR[DMI]+2774h"
to fully enable the Lpc IO enable decoding which is missing in
current source.
Without above changes, Skylake Saddlebrook platform with a
SIO does not boot.
Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173
Signed-off-by: praveen <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/22819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/fizz')
0 files changed, 0 insertions, 0 deletions