skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI

Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")

This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.

BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.

Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 27 insertions, 15 deletions

diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index ae952862e8..330ba4eee2 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -49,13 +49,14 @@ static const struct pad_config gpio_table[] = {
 /* CLKOUT_LPC1 */	PAD_CFG_NC(GPP_A10), /* TP188 */
 /* PME# */		PAD_CFG_NC(GPP_A11), /* TP149 */
 /* BM_BUSY# */		PAD_CFG_NC(GPP_A12),
-/* SUSWARN# */		PAD_CFG_GPI(GPP_A13, NONE, DEEP), /* eSPI mode */
+/* SUSWARN# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,
+						DEEP), /* eSPI mode */
 /* ESPI_RESET# */
 /* SUSACK# */		PAD_CFG_NC(GPP_A15), /* TP150 */
 /* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 /* SD_PWR_EN# */	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
 /* ISH_GP0 */		PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */
-/* ISH_GP1 */		PAD_CFG_GPI(GPP_A19, NONE, DEEP), /* HDPO */
+/* ISH_GP1 */		PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */
 /* ISH_GP2 */		PAD_CFG_NC(GPP_A20),
 /* ISH_GP3 */		PAD_CFG_NC(GPP_A21),
 /* ISH_GP4 */		PAD_CFG_NC(GPP_A22),
@@ -96,8 +97,10 @@ static const struct pad_config gpio_table[] = {
 /* GSPI0_MOSI */	PAD_CFG_NC(GPP_B18),
 #endif
 /* GSPI1_CS# */		PAD_CFG_NC(GPP_B19), /* TP111 */
-/* GSPI1_CLK */		PAD_CFG_GPI(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */
-/* GSPI1_MISO */	PAD_CFG_GPI(GPP_B21, 20K_PU, DEEP), /* HWA_TRST_N */
+/* GSPI1_CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU,
+						DEEP), /* VR_DISABLE_L */
+/* GSPI1_MISO */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU,
+						DEEP), /* HWA_TRST_N */
 /* GSPI1_MOSI */	PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */
 /* SML1ALERT# */		PAD_CFG_NC(GPP_B23), /* TP141 */
 
@@ -107,16 +110,25 @@ static const struct pad_config gpio_table[] = {
 /* SML0CLK */		PAD_CFG_NC(GPP_C3),
 /* SML0DATA */		PAD_CFG_NC(GPP_C4),
 /* SML0ALERT# */	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
-/* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
+/* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,
+						DEEP), /* EC_IN_RW */
 /* SM1DATA */		PAD_CFG_NC(GPP_C7), /* TP310 */
-/* UART0_RXD */		PAD_CFG_GPI(GPP_C8, 20K_PU, DEEP), /* GPIO1 */
-/* UART0_TXD */		PAD_CFG_GPI(GPP_C9, 20K_PU, DEEP), /* GPIO2 */
-/* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, 20K_PU, DEEP), /* GPIO3 */
-/* UART0_CTS# */	PAD_CFG_GPI(GPP_C11, 20K_PU, DEEP), /* GPIO4 */
-/* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* SKU_ID0 */
-/* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* SKU_ID1 */
-/* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* SKU_ID2 */
-/* UART1_CTS# */	PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* SKU_ID3 */
+/* UART0_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU,
+							DEEP), /* GPIO1 */
+/* UART0_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU,
+							DEEP), /* GPIO2 */
+/* UART0_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU,
+						DEEP), /* GPIO3 */
+/* UART0_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU,
+						DEEP), /* GPIO4 */
+/* UART1_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
+							DEEP), /* SKU_ID0 */
+/* UART1_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
+							DEEP), /* SKU_ID1 */
+/* UART1_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
+						DEEP), /* SKU_ID2 */
+/* UART1_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
+						DEEP), /* SKU_ID3 */
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 #if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)
@@ -131,7 +143,7 @@ static const struct pad_config gpio_table[] = {
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_RTS# */	PAD_CFG_NC(GPP_C22), /* TP309 */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, NONE,
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
 				    DEEP), /* SCREW_SPI_WP_STATUS */
 
 /* SPI1_CS# */		PAD_CFG_NC(GPP_D0), /* TP259 */
@@ -270,7 +282,7 @@ static const struct pad_config early_gpio_table[] = {
 /* Ensure UART pins are in native mode for H1. */
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, NONE,
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
 				    DEEP), /* SCREW_SPI_WP_STATUS */
 };