diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 03:39:24 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:44:02 +0000 |
| commit | dcddc53fde2d559beef998d3c17e9b7a227e3665 (patch) | |
| tree | f3061a3764892f73bc5dd827134a795c275b685f /src/mainboard/google/fizz/variants | |
| parent | 6c83a71b0a803c922b02b613e927d4c49b944c32 (diff) | |
skl mainboards/dt: Move genx_dec settings into LPC device scope
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fizz/variants')
| -rw-r--r-- | src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index a6ec6b62f8..7d11653ff7 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -52,12 +52,6 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -407,6 +401,12 @@ chip soc/intel/skylake end device ref sdxc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end |