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authorShelley Chen <shchen@chromium.org>2017-03-15 15:25:48 -0700
committerMartin Roth <martinroth@google.com>2017-03-23 19:58:24 +0100
commit243dc3913df4bc112e074931c7726a6eb21273c6 (patch)
tree74aaec53555eee5502cfcf253a3ebc6f79cfe375 /src/mainboard/google/fizz/smihandler.c
parent7de031759b916bbb91e74e6eea371b5ca87e6bd5 (diff)
google/fizz: Add new board
Creating google/fizz directory based on poppy (using kabylake and FSP 2.0). Only making name changes and Copyright year changes. Many poppy-specific configs left in and will be updated in follup CLs. BUG=b:35775024 BRANCH=None TEST=Compile fizz board Change-Id: Icab3639a53fef65e904e797028916fda879fff7c Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/18796 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz/smihandler.c')
-rw-r--r--src/mainboard/google/fizz/smihandler.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c
new file mode 100644
index 0000000000..d7ef5093f8
--- /dev/null
+++ b/src/mainboard/google/fizz/smihandler.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <soc/smm.h>
+
+#include "ec.h"
+
+void mainboard_smi_espi_handler(void)
+{
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}