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authorShelley Chen <shchen@chromium.org>2017-03-15 15:25:48 -0700
committerMartin Roth <martinroth@google.com>2017-03-23 19:58:24 +0100
commit243dc3913df4bc112e074931c7726a6eb21273c6 (patch)
tree74aaec53555eee5502cfcf253a3ebc6f79cfe375 /src/mainboard/google/fizz/mainboard.c
parent7de031759b916bbb91e74e6eea371b5ca87e6bd5 (diff)
google/fizz: Add new board
Creating google/fizz directory based on poppy (using kabylake and FSP 2.0). Only making name changes and Copyright year changes. Many poppy-specific configs left in and will be updated in follup CLs. BUG=b:35775024 BRANCH=None TEST=Compile fizz board Change-Id: Icab3639a53fef65e904e797028916fda879fff7c Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/18796 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz/mainboard.c')
-rw-r--r--src/mainboard/google/fizz/mainboard.c79
1 files changed, 79 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
new file mode 100644
index 0000000000..0cd0643848
--- /dev/null
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static const char *oem_id_maxim = "GOOGLE";
+static const char *oem_table_id_maxim = "FIZZMAX";
+
+static void mainboard_init(device_t dev)
+{
+ mainboard_ec_init();
+}
+
+static unsigned long mainboard_write_acpi_tables(device_t device,
+ unsigned long current, acpi_rsdp_t *rsdp)
+{
+ uintptr_t start_addr;
+ uintptr_t end_addr;
+ struct nhlt *nhlt;
+
+ start_addr = current;
+
+ nhlt = nhlt_init();
+
+ if (nhlt == NULL)
+ return start_addr;
+
+ /* 2 Channel DMIC array. */
+ if (nhlt_soc_add_dmic_array(nhlt, 2))
+ printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
+
+ /* 4 Channel DMIC array. */
+ if (nhlt_soc_add_dmic_array(nhlt, 4))
+ printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
+
+ /* Maxim MAX98927 Smart Amps for left and right channel */
+ if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0))
+ printk(BIOS_ERR, "Couldn't add Maxim MAX98927\n");
+
+ /* Realtek RT5663 Headset codec. */
+ if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1))
+ printk(BIOS_ERR, "Couldn't add Realtek RT5663.\n");
+
+ end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
+ oem_id_maxim, oem_table_id_maxim, 0);
+
+ if (end_addr != start_addr)
+ acpi_add_table(rsdp, (void *)start_addr);
+
+ return end_addr;
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};