mb/google/{poppy,eve,fizz}: Configure GPIOs in mainboard chip->init()

mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().

Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 48 insertions, 0 deletions

diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index 89e692741e..6a7d452942 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -16,6 +16,7 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <chip.h>
+#include <delay.h>
 #include <device/device.h>
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
@@ -26,8 +27,11 @@
 #include <soc/pci_devs.h>
 #include <soc/nhlt.h>
 #include <string.h>
+#include <timer.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+#include <variant/gpio.h>
+
 #define FIZZ_SKU_ID_I7_U42  0x4
 #define FIZZ_SKU_ID_I5_U42  0x5
 #define FIZZ_SKU_ID_I3_U42  0x6
@@ -230,6 +234,50 @@ static void mainboard_enable(struct device *dev)
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 }
 
+#define GPIO_HDMI_HPD		GPP_E13
+#define GPIO_DP_HPD		GPP_E14
+
+/* TODO: This can be moved to common directory */
+static void wait_for_hpd(gpio_t gpio, long timeout)
+{
+	struct stopwatch sw;
+
+	printk(BIOS_INFO, "Waiting for HPD\n");
+	gpio_input(gpio);
+
+	stopwatch_init_msecs_expire(&sw, timeout);
+	while (!gpio_get(gpio)) {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_WARNING,
+			       "HPD not ready after %ldms. Abort.\n", timeout);
+			return;
+		}
+		mdelay(200);
+	}
+	printk(BIOS_INFO, "HPD ready after %lu ms\n",
+	       stopwatch_duration_msecs(&sw));
+}
+
+static void mainboard_chip_init(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+	static const long display_timeout_ms = 3000;
+
+	/* This is reconfigured back to whatever FSP-S expects by
+	   gpio_configure_pads. */
+	gpio_input(GPIO_HDMI_HPD);
+	if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) {
+		/* This has to be done before FSP-S runs. */
+		if (google_chromeec_wait_for_displayport(display_timeout_ms))
+			wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
+	}
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
+
 struct chip_operations mainboard_ops = {
+	.init = mainboard_chip_init,
 	.enable_dev = mainboard_enable,
 };