diff options
| author | Shelley Chen <shchen@chromium.org> | 2017-06-09 12:56:08 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-20 03:16:34 +0200 |
| commit | db287aad2547d6bc4a710c8a511448b5ff5ebead (patch) | |
| tree | 48719a2e3479be1e70f86aa1cbe7cb39c60a068d /src/mainboard/google/fizz/gpio.h | |
| parent | 1b5eda02332db0182b282a2afc960d6899c0b31a (diff) | |
google/fizz: Enable cr50 over i2c
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure verstage doesn't have any TPM errors
CQ-DEPEND=CL:530185
Change-Id: Icfde0f62bd058d960fcb0c6fc67f9d8f6b9462f5
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20133
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fizz/gpio.h')
| -rw-r--r-- | src/mainboard/google/fizz/gpio.h | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index ced33e97b0..9f7da49ed4 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -108,8 +108,15 @@ static const struct pad_config gpio_table[] = { /* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, + NF1), /* PCH_I2C1_H1_3V3_SDA */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, + NF1), /* PCH_I2C1_H1_3V3_SCL */ +#else +/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +#endif /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ @@ -231,10 +238,12 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, - NF1), /* PCH_I2C2_H1_3V3_SDA */ -/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, - NF1), /* PCH_I2C2_H1_3V3_SCL */ +#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, + NF1), /* PCH_I2C1_H1_3V3_SDA */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, + NF1), /* PCH_I2C1_H1_3V3_SCL */ +#endif /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ |