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authorShelley Chen <shchen@chromium.org>2017-06-09 12:56:08 -0700
committerMartin Roth <martinroth@google.com>2017-06-20 03:16:34 +0200
commitdb287aad2547d6bc4a710c8a511448b5ff5ebead (patch)
tree48719a2e3479be1e70f86aa1cbe7cb39c60a068d /src/mainboard/google/fizz/devicetree.cb
parent1b5eda02332db0182b282a2afc960d6899c0b31a (diff)
google/fizz: Enable cr50 over i2c
BUG=b:62456589, b:35775024 BRANCH=None TEST=Reboot and ensure verstage doesn't have any TPM errors CQ-DEPEND=CL:530185 Change-Id: Icfde0f62bd058d960fcb0c6fc67f9d8f6b9462f5 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20133 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fizz/devicetree.cb')
-rw-r--r--src/mainboard/google/fizz/devicetree.cb14
1 files changed, 13 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index ff2ec7f86d..abd5452f21 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -181,6 +181,12 @@ chip soc/intel/skylake
register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
+ # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
+ # for TPM communication before memory is up.
+ register "i2c[1]" = "{
+ .early_init = 1,
+ }"
+
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@@ -214,7 +220,13 @@ chip soc/intel/skylake
device pci 14.2 on end # Thermal Subsystem
device pci 15.0 on
end # I2C #0
- device pci 15.1 on end # I2C #1
+ device pci 15.1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
+ device i2c 50 on end
+ end
+ end # I2C #1
device pci 15.2 on end # I2C #2
device pci 15.3 off
end # I2C #3