diff options
| author | Tsai, Gaggery <gaggery.tsai@intel.com> | 2017-08-22 10:55:13 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-02 15:32:03 +0000 |
| commit | b2a3ac4705a4e0ad63d0699b8ded8991e5979b84 (patch) | |
| tree | cfd9b00c1f564ccf5535b6e95dd3b2ce8a7d198e /src/mainboard/google/fizz/devicetree.cb | |
| parent | 3f12d9321ac9d7ea6a4609aec697760c658af6f9 (diff) | |
mainboard/google/fizz: Enable support for DPTF
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for fizz.
It also enables the DPTF flag in the device tree for fizz.
BUG=b:64915426
BRANCH=None
TEST=emerge-fizz coreboot and run DPTF observation tool to make sure
DPTF is up and running.
Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca
Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/fizz/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a771380238..ead880e445 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -21,6 +21,9 @@ chip soc/intel/skylake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "1" |