diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2018-09-13 16:51:14 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-19 09:23:23 +0000 |
| commit | aceaa71531e39042d98c6029313fc7d49a4c1d2b (patch) | |
| tree | d55ce389d3eaf9b01b36f5549a1e7a5176533164 /src/mainboard/google/fizz/acpi | |
| parent | 8f45bf2be71ee5608dfda57b5a6ee8a9e909250a (diff) | |
mb/google/fizz: Provide baseboard and variant concepts
In order to be able to share code across different fizz variants,
provide the concept of baseboard and variants. New directory layout:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/fizz - code
variants/fizz/include/variant - headers
New boards would then add themselves under their board name within
"variants" directory.
This is purely an organizational change.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
CQ-DEPEND=CL:1273514
Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz/acpi')
| -rw-r--r-- | src/mainboard/google/fizz/acpi/dptf.asl | 72 |
1 files changed, 0 insertions, 72 deletions
diff --git a/src/mainboard/google/fizz/acpi/dptf.asl b/src/mainboard/google/fizz/acpi/dptf.asl deleted file mode 100644 index f877c71c03..0000000000 --- a/src/mainboard/google/fizz/acpi/dptf.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 93 -#define DPTF_CPU_CRITICAL 100 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 77 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 70 -#define DPTF_TSR0_CRITICAL 83 -#define DPTF_TSR0_ACTIVE_AC0 95 -#define DPTF_TSR0_ACTIVE_AC1 85 -#define DPTF_TSR0_ACTIVE_AC2 60 -#define DPTF_TSR0_ACTIVE_AC3 52 -#define DPTF_TSR0_ACTIVE_AC4 44 -#define DPTF_TSR0_ACTIVE_AC5 38 -#define DPTF_TSR0_ACTIVE_AC6 35 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR1_PASSIVE 67 -#define DPTF_TSR1_CRITICAL 73 - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 44000, /* PowerLimitMinimum */ - 44000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) - -/* Include DPTF */ -#include <soc/intel/skylake/acpi/dptf/dptf.asl> |