diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2021-10-07 18:11:12 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-11 12:57:18 +0000 |
| commit | 8feb8669dd09b122bc92b2afcf3794afc40a6df2 (patch) | |
| tree | 4d51276132f658f65f4df01f93fd578fe5ec1c7b /src/mainboard/google/fizz/acpi | |
| parent | ff1ef8db4a383ff04d6ca4c4c464a06055f51137 (diff) | |
mb/google/fizz: Drop broken USB ACPI code
Fizz's USB ACPI code is intended to allow the OS to control port
charging power, but since Fizz's ports are dumb (vs smart), it
controls power to the port itself. The end result is that active
ports become disabled when rebooting from Windows (10/11), and
power is not restored until the device is powered down (a warm
reboot is not sufficient).
Subsequent Chromebox models (eg, Puff-based variants) don't bother
with EC-controlled USB port power, so just drop it since it's
problematic and provides no benefit.
Test: boot Windows 10/11, reboot, observe active USB ports still
functional (eg, USB KB still works)
Change-Id: I2c13d49b3ce8de8b0a38512db3c57d0c8ecbf0ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/google/fizz/acpi')
| -rw-r--r-- | src/mainboard/google/fizz/acpi/usb.asl | 112 |
1 files changed, 0 insertions, 112 deletions
diff --git a/src/mainboard/google/fizz/acpi/usb.asl b/src/mainboard/google/fizz/acpi/usb.asl deleted file mode 100644 index 1aa145ffe6..0000000000 --- a/src/mainboard/google/fizz/acpi/usb.asl +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.XHCI.RHUB.HS02) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (2) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (2) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.HS03) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (3) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (3) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.HS04) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (4) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (4) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.HS05) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (0) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (0) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.HS06) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (1) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (1) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS02) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (2) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (2) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS03) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (3) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (3) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS04) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (4) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (4) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS05) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (0) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (0) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS06) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (1) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (1) - } -} |