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authorCliff Huang <cliff.huang@intel.com>2024-10-10 00:56:34 -0700
committerSubrata Banik <subratabanik@google.com>2024-10-17 04:35:38 +0000
commitdd1ca85dd3e43771b91880c9effab31f48569dff (patch)
treeb78a806dc428522d0146891d6eb39feb15236216 /src/mainboard/google/fatcat
parent7d569573958f29d1aef80f023e92ac40ad9c9f86 (diff)
mb/google/fatcat: add pre-mem configuration based on fw_config
Add the GPIO pad configuration to be performed before memory is set up along with the relevant devices definition. This patch includes: - FW config for pre-mem GPIO PAD configuration - Add overridetree changes used by pre-mem FW config BUG=b:348678529 TEST=Boot on Google Fatcat board. Note this cannot be tested by itself directly. Test with CL:84408, set the proper CBI fw_config bit(s) and check that the corresponding GPIO PADs are configured as expected value accordingly. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/84718 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
Diffstat (limited to 'src/mainboard/google/fatcat')
-rw-r--r--src/mainboard/google/fatcat/Kconfig1
-rw-r--r--src/mainboard/google/fatcat/romstage.c15
-rw-r--r--src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h1
-rw-r--r--src/mainboard/google/fatcat/variants/fatcat/Makefile.mk1
-rw-r--r--src/mainboard/google/fatcat/variants/fatcat/fw_config.c108
-rw-r--r--src/mainboard/google/fatcat/variants/fatcat/overridetree.cb281
6 files changed, 405 insertions, 2 deletions
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 15608212cc..6d3f4959c7 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_FATCAT_COMMON
select DRIVERS_INTEL_MIPI_CAMERA
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_SOUNDWIRE
+ select DRIVERS_WWAN_FM350GL
select DRIVERS_SOUNDWIRE_ALC722
select DRIVERS_SPI_ACPI
select DUMP_SMBIOS_TYPE17
diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 9e41d4660e..7b56e28e3c 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -5,6 +5,17 @@
#include <soc/romstage.h>
#include <string.h>
+/*
+ * Placeholder to configure GPIO early from romstage relying on the FW_CONFIG.
+ *
+ * If any platform would like to override early GPIOs, they should override from
+ * the variant directory.
+ */
+__weak void fw_config_configure_pre_mem_gpio(void)
+{
+ /* Nothing to do */
+}
+
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct pad_config *pads;
@@ -14,7 +25,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
struct mem_spd spd_info;
pads = variant_romstage_gpio_table(&pads_num);
- gpio_configure_pads(pads, pads_num);
+ if (pads_num)
+ gpio_configure_pads(pads, pads_num);
+ fw_config_configure_pre_mem_gpio();
memset(&spd_info, 0, sizeof(spd_info));
variant_get_spd_info(&spd_info);
diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
index 27fd8b72e8..581ba5135c 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
@@ -16,6 +16,7 @@
const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);
const struct pad_config *variant_romstage_gpio_table(size_t *num);
+void fw_config_configure_pre_mem_gpio(void);
void fw_config_gpio_padbased_override(struct pad_config *padbased_table);
const struct mb_cfg *variant_memory_params(void);
diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
index 88986e4814..ac6779c131 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
@@ -3,5 +3,6 @@
bootblock-y += gpio.c
romstage-y += gpio.c
romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-y += gpio.c
ramstage-y += variant.c
diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
new file mode 100644
index 0000000000..0e34c13201
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootstate.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+#define GPIO_CONFIGURE_PADS(a) gpio_configure_pads(a, ARRAY_SIZE(a))
+
+static const struct pad_config pre_mem_x1slot_pads[] = {
+ /* GPP_A08: X1_PCIE_SLOT_PWR_EN */
+ PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+};
+
+/*
+ * WWAN: power sequence requires three stages:
+ * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
+ * step 2: deassert FCP#
+ * step 3: deassert RST# first, and then PERST#.
+ * NOTE: Since PERST# is gated by platform reset, PERST# deassertion will happen
+ * at much later time and time between RST# and PERSET# is guaranteed.
+ */
+static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = {
+ /* GPP_H16: WWAN_PWREN */
+ PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+ /* GPP_A09: M.2_WWAN_FCP_OFF_N */
+ PAD_CFG_GPO(GPP_A09, 0, PLTRST),
+ /* GPP_B20: M.2_WWAN_RST_N */
+ PAD_CFG_GPO(GPP_B20, 0, PLTRST),
+ /* GPP_D03: M.2_WWAN_PERST_GPIO_N */
+ PAD_CFG_GPO(GPP_D03, 0, PLTRST),
+};
+
+static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = {
+ /* GPP_A09: M.2_WWAN_FCP_OFF_N */
+ PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+};
+
+/* gen4 NVME: at the top M.2 slot */
+static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
+ /* GPP_B10: GEN4_SSD_PWREN */
+ PAD_CFG_GPO(GPP_B10, 0, PLTRST),
+};
+
+/* gen5 NVME: at the bottom M.2 slot */
+static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
+ /* GPP_B16: GEN5_SSD_PWREN */
+ PAD_CFG_GPO(GPP_B16, 0, PLTRST),
+};
+
+/* camera1: WFC */
+static const struct pad_config pre_mem_wfc_camera_pwr_pads[] = {
+ /* GPP_C05: CRD1_PWREN */
+ PAD_CFG_GPO(GPP_C05, 0, PLTRST),
+};
+
+/* camera2: UFC */
+static const struct pad_config pre_mem_ufc_camera_pwr_pads[] = {
+ /* GPP_C08: CRD2_PWREN */
+ PAD_CFG_GPO(GPP_C08, 0, PLTRST),
+};
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+ if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) ||
+ fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) {
+ GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
+ }
+
+ if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) {
+ GPIO_CONFIGURE_PADS(pre_mem_wfc_camera_pwr_pads);
+ }
+
+ if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) {
+ GPIO_CONFIGURE_PADS(pre_mem_ufc_camera_pwr_pads);
+ }
+
+ if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+ GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+ } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
+ GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
+ } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+ /* TODO */
+ } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+ GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+ GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
+ /* TODO for UFS */
+ }
+
+ if (fw_config_probe(FW_CONFIG(SD, SD_GENSYS)) ||
+ fw_config_probe(FW_CONFIG(SD, SD_BAYHUB))) {
+ GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
+ }
+ /*
+ * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
+ * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
+ * and FCP#) is '0'. Therefore, it will be fine even though there is no
+ * GPIO configured for other PADs via fw_config to have the time delay
+ * introduced in between sequence 1 and 2. Also, FCP# was not the last PAD
+ * configured in sequence 1. Although the Tpr is '0' in the datasheet, three
+ * stages are preserved at this time to guarantee the sequence shown in the
+ * datasheet timing diagram.
+ */
+ if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) ||
+ fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) {
+ GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads);
+ }
+}
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 623a332c7b..f89bfd8783 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -65,5 +65,284 @@ fw_config
end
chip soc/intel/pantherlake
- device domain 0 on end
+
+ register "serial_io_i2c_mode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ }"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| I2C1 | Camera(CRD1) |
+ #| I2C2 | Camera(CRD2) |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
+ device domain 0 on
+ device ref ipu on
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "0x50000"
+ register "acpi_name" = ""IPU0""
+ register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+ register "cio2_num_ports" = "2"
+ register "cio2_lanes_used" = "{4,2}"
+ register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0""
+ register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
+ register "cio2_prt[0]" = "0"
+ register "cio2_prt[1]" = "2"
+ device generic 0 on end
+ end
+ end
+
+ device ref pcie_rp2 on
+ probe CELLULAR CELLULAR_PCIE
+ register "pcie_rp[PCIE_RP(2)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
+ register "reset_off_delay_ms" = "20"
+ register "srcclk_pin" = "5"
+ register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+ register "skip_on_off_support" = "true"
+ register "use_rp_mutex" = "true"
+ device generic 0 alias rp2_rtd3 on
+ probe CELLULAR CELLULAR_PCIE
+ end
+ end
+ chip drivers/wwan/fm
+ register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)"
+ register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
+ register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)"
+ register "add_acpi_dma_property" = "true"
+ use rp2_rtd3 as rtd3dev
+ device generic 0 on
+ probe CELLULAR CELLULAR_PCIE
+ end
+ end
+ end # WWAN
+ device ref pcie_rp3 on
+ probe SD SD_GENSYS
+ probe SD SD_BAYHUB
+ # Enable PCH PCIE x1 slot using CLK 3
+ register "pcie_rp[PCIE_RP(3)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
+ register "enable_delay_ms" = "100"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+ register "reset_delay_ms" = "20"
+ register "srcclk_pin" = "2"
+ device generic 0 on
+ probe SD SD_GENSYS
+ probe SD SD_BAYHUB
+ end
+ end
+ end # PCIE x1 slot
+ device ref pcie_rp5 on
+ probe STORAGE STORAGE_NVME_GEN4
+ probe STORAGE STORAGE_UNKNOWN
+ register "pcie_rp[PCIE_RP(5)]" = "{
+ .clk_src = 6,
+ .clk_req = 6,
+ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "is_storage" = "true"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+ register "srcclk_pin" = "6"
+ device generic 0 on
+ probe STORAGE STORAGE_NVME_GEN4
+ probe STORAGE STORAGE_UNKNOWN
+ end
+ end
+ end # Gen4 M.2 SSD
+ device ref pcie_rp9 on
+ probe STORAGE STORAGE_NVME_GEN5
+ probe STORAGE STORAGE_UNKNOWN
+ register "pcie_rp[PCIE_RP(9)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "is_storage" = "true"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
+ register "srcclk_pin" = "1"
+ device generic 0 on
+ probe STORAGE STORAGE_NVME_GEN5
+ probe STORAGE STORAGE_UNKNOWN
+ end
+ end
+ end # Gen5 M.2 SSD
+
+ # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+ # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
+ device ref i2c0 on end
+ device ref i2c1 on
+ probe WFC WFC_MIPI
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = ""OVTIDB10""
+ register "acpi_uid" = "0"
+ register "acpi_name" = ""CAM0""
+ register "chip_name" = ""Ov 13b10 Camera""
+ register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+ register "ssdb.vcm_type" = "0x0C"
+ register "vcm_name" = ""VCM1""
+
+ register "ssdb.lanes_used" = "4"
+ register "num_freq_entries" = "1"
+ register "link_freq[0]" = "560000000"
+ register "remote_name" = ""IPU0""
+
+ register "has_power_resource" = "1"
+ #Controls
+ register "clk_panel.clks[0].clknum" = "0"
+ register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset
+
+ #_ON
+ register "on_seq.ops_cnt" = "4"
+ register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+ register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "3"
+ register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+ device i2c 36 on
+ probe WFC WFC_MIPI
+ end
+ end
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "3"
+ register "acpi_name" = ""VCM1""
+ register "chip_name" = ""DW AF VCM""
+ register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+ register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
+ register "vcm_compat" = ""dongwoon,dw9714""
+
+ device i2c 0C on
+ probe WFC WFC_MIPI
+ end
+ end
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "1"
+ register "acpi_name" = ""NVM1""
+ register "chip_name" = ""BRCA016GWZ""
+ register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+ register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
+ register "nvm_compat" = ""atmel,24c16""
+
+ register "nvm_size" = "0x800"
+ register "nvm_pagesize" = "0x01"
+ register "nvm_readonly" = "0x01"
+ register "nvm_width" = "0x08"
+
+ device i2c 50 on
+ probe WFC WFC_MIPI
+ end
+ end
+ end
+ device ref i2c2 on
+ probe UFC UFC_MIPI
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = ""OVTIDB10""
+ register "acpi_uid" = "0"
+ register "acpi_name" = ""CAM1""
+ register "chip_name" = ""Ov 13b10 Camera""
+ register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+ register "ssdb.vcm_type" = "0x0C"
+ register "vcm_name" = ""VCM1""
+
+ register "ssdb.lanes_used" = "2"
+ register "num_freq_entries" = "1"
+ register "link_freq[0]" = "560000000"
+ register "remote_name" = ""IPU0""
+
+ register "has_power_resource" = "1"
+ #Controls
+ register "clk_panel.clks[0].clknum" = "1"
+ register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset
+
+ #_ON
+ register "on_seq.ops_cnt" = "4"
+ register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+ register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "3"
+ register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+ device i2c 36 on
+ probe UFC UFC_MIPI
+ end
+ end
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "3"
+ register "acpi_name" = ""VCM1""
+ register "chip_name" = ""DW AF VCM""
+ register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+ register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC""
+ register "vcm_compat" = ""dongwoon,dw9714""
+
+ device i2c 0C on
+ probe UFC UFC_MIPI
+ end
+ end
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "1"
+ register "acpi_name" = ""NVM1""
+ register "chip_name" = ""BRCA016GWZ""
+ register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+ register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC""
+ register "nvm_compat" = ""atmel,24c16""
+
+ register "nvm_size" = "0x800"
+ register "nvm_pagesize" = "0x01"
+ register "nvm_readonly" = "0x01"
+ register "nvm_width" = "0x08"
+
+ device i2c 50 on
+ probe UFC UFC_MIPI
+ end
+ end
+ end
+ end
end