diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-10-30 00:22:28 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-10-31 03:35:34 +0000 |
| commit | 28717bd0d3eac7c4e6ffa42d6f7b8f2aa2603ece (patch) | |
| tree | 13fe675a0c8930f56ab2b7943d59f04245a942ba /src/mainboard/google/fatcat | |
| parent | bc8cc460550364c16ae00b00e19fd8c033ec175c (diff) | |
mb/google/fatcat: Adjust EC host command range for microchip EC
This commit adjusts the EC host command range for the Fatcat board to
0x800-0x807 & 0x200-0x20f.
This change is necessary because the microchip EC used on the Fatcat
board has a smaller host command range than the ITE/Nuvoton ECs used
on other Fatcat variants.
The `gen1_dec` register in the devicetree is updated to reflect this
change.
As per boot log, the `gen1_dec` aka offset 0x84, base address is 800
and size is 8 bytes.
AP FW Boot log:
[SPEW] PCI: 00:00:1f.0 resource base 800 size 8 align 0 gran 0 limit 0 flags c0000100 index 84
BUG=b:376207365
TEST=Able to build and boot google/fatcat w/o any error.
without this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
[ERROR] LPC: Cannot open IO window: 800 size 8
[ERROR] No more IO windows
with this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84919
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Diffstat (limited to 'src/mainboard/google/fatcat')
| -rw-r--r-- | src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index d794925f2a..1b1fc73df9 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -4,8 +4,11 @@ chip soc/intel/pantherlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" + # For Fatcat (with microchip EC): + # EC host command ranges are in 0x800-0x807 & 0x200-0x20f + # For other Fatcat variants (with ITE/Nuvoton EC): + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "CONFIG(BOARD_GOOGLE_FATCAT) ? 0x00040801 : 0x00fc0801" register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" |