diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-06-25 00:17:56 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-06-26 22:30:42 +0000 |
| commit | 3aea34a9933f7884a2c08b9611f7b3ff9d791b1d (patch) | |
| tree | 4de5afb69b07e9db7db5ef700a38d8fdded20ff2 /src/mainboard/google/fatcat/chromeos-debug-fsp.fmd | |
| parent | f3aaa0e1539c16a3a26a769110ec1aca458ab410 (diff) | |
mb/google/fatcat: Add minimal code support for fatcat
This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google/fatcat/chromeos-debug-fsp.fmd')
| -rw-r--r-- | src/mainboard/google/fatcat/chromeos-debug-fsp.fmd | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd new file mode 100644 index 0000000000..5b20f00018 --- /dev/null +++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd @@ -0,0 +1,49 @@ +FLASH 32M { + SI_ALL 8M { + SI_DESC 16K + SI_ME + } + SI_BIOS 24M { + RW_SECTION_A 7680K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7680K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 3M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} |