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authorVladimir Serbinenko <phcoder@gmail.com>2014-10-31 09:16:31 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2015-05-28 08:27:10 +0200
commitdd2bc3f819ecb64a07f37c2a63621ecadd6b6ed8 (patch)
treef611f100b307a2acc410a99726825e736d958e40 /src/mainboard/google/falco
parentf44ac13db26c5ab18ac2e35111acbf91841a2608 (diff)
igd.asl rewrite
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Diffstat (limited to 'src/mainboard/google/falco')
-rw-r--r--src/mainboard/google/falco/acpi_tables.c7
-rw-r--r--src/mainboard/google/falco/devicetree.cb3
2 files changed, 3 insertions, 7 deletions
diff --git a/src/mainboard/google/falco/acpi_tables.c b/src/mainboard/google/falco/acpi_tables.c
index 238b48d0fd..8a6ef01320 100644
--- a/src/mainboard/google/falco/acpi_tables.c
+++ b/src/mainboard/google/falco/acpi_tables.c
@@ -60,13 +60,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb
index 7a8e757877..8cdb0325d3 100644
--- a/src/mainboard/google/falco/devicetree.cb
+++ b/src/mainboard/google/falco/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/haswell
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"