diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-17 15:49:58 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-25 17:58:08 +0000 |
| commit | c204aaa23b8455457920a56a85b0128f9818f461 (patch) | |
| tree | aab5c43aae02df5f04ccea3d903a04d887012c9d /src/mainboard/google/eve | |
| parent | bcefbe163f70ef2590be252057d626e788047b16 (diff) | |
soc/intel/skylake: Add LPC and SPI lock down config option
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/eve')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index b6cb848b40..2e017f8dcd 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -218,6 +218,9 @@ chip soc/intel/skylake register "tdp_pl2_override" = "15" register "tcc_offset" = "10" + # Lock Down + register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + device cpu_cluster 0 on device lapic 0 on end end |