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authorJulius Werner <jwerner@chromium.org>2021-02-24 16:58:17 -0800
committerPatrick Georgi <pgeorgi@google.com>2021-02-26 08:18:28 +0000
commita89406e7f723e73762c672e9365c506fb3052047 (patch)
tree4dc85ef4557f4f79360dc610645139d2e685c40a /src/mainboard/google/eve
parentc7762466b3027396dd07cd79999bae26a70885eb (diff)
rk3399: clock: Fix style for rkclk_ddr_reset()
This function should be using the RK_CLRSETBITS() macros to access the special Rockchip write-mask registers, like the rest of our code. Also, there were already existing bit field definitions for these bits that should be used (although it makes sense to adjust them a bit to allow passing in the channel number). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If1f5c06aabb16045d890df3bbd271f08a2cdf390 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51080 Reviewed-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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