diff options
| author | Duncan Laurie <dlaurie@google.com> | 2017-11-01 13:23:45 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-11-14 21:21:40 +0000 |
| commit | d60b4930bb1493a74a1eb65b5d0a73a9483e4c4c (patch) | |
| tree | 3afc16b06338384f9bc8f43a8a65df51cd41e458 /src/mainboard/google/eve | |
| parent | bfd17e34219f71e3cca458648997cb2f8f5ee2ca (diff) | |
mb/google/eve: Enable VMX
This feature was enabled at the kernel level, but that is triggering an
issue where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot. Since we want this enabled anyway just set it this
way in the BIOS so it matches what the kernel expects.
BUG=b:68666100
TEST=pass firmware_FWtries on Eve with R63 OS image
Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/749733
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/eve')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 50926da29a..3d1077b5e1 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -53,6 +53,7 @@ chip soc/intel/skylake register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" |