diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-09-18 14:21:48 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-11-14 21:21:33 +0000 |
| commit | ebd67c23ed107d0f43c54a0d01286c90bfccd299 (patch) | |
| tree | 3f557c2992fe41ab42fa612c4cb23e2f0da565fa /src/mainboard/google/eve | |
| parent | f8e4eb84e571a19ac983ee3661dee2e95bdc184c (diff) | |
mb/google/eve: Enable AER and LTR
AER and LTR must be enabled individually on ports that need it,
in this case it should be enabled for WiFi and NVMe.
BUG=b:65457528
TEST=Wifi team verified that the performance is better with these changes.
Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/671211
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/eve')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 069c2b0b69..3b87fd17b5 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -143,11 +143,15 @@ chip soc/intel/skylake register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" # Enable Root port 5 with SRCCLKREQ4# register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |