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author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-03 17:54:56 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-06 16:03:31 +0000 |
commit | 4b679b06480e5897c6120b8e72ea755c57af2593 (patch) | |
tree | 5c2894edd5299588cee6585387e0303f18fb4afb /src/mainboard/google/eve/dsdt.asl | |
parent | cc34162734b4d924012102210095bcf8903ea758 (diff) |
soc/amd/picasso/acpi: don't announce unimplemented duty cycle control
Picasso neither has the corresponding P_CNT register implemented nor
writes a _PTC ACPI object that would specify the P_CNT register. The
Picasso UEFI reference code also sets the duty_width FADT entry to 0.
This also aligns the Picasso code with the Cezanne code in this regard.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I74645e5c4e54a2ad6bc7f9e72f5f656027a79860
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/mainboard/google/eve/dsdt.asl')
0 files changed, 0 insertions, 0 deletions