diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-02-11 12:02:40 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-02-16 08:42:38 +0100 |
| commit | 231c198e2ce56741c945149a6c553b1f4e81a4e2 (patch) | |
| tree | 8f1b35fa5c50e549c0f71fbdae1331b0d05268cb /src/mainboard/google/eve/devicetree.cb | |
| parent | 20a91c9830eaa74ee58cfccb59193671949eb086 (diff) | |
mainboard/google/eve: Generate FPC device using SPI SSDT generator
Use the newly added SPI SSDT generator for adding FPC device.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully. Verified that the SSDT entry matches the
entry in mainboard.asl
Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18343
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/eve/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 8a6764237b..3321565f52 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -255,7 +255,15 @@ chip soc/intel/skylake device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""fpc,fpc1020"" + register "irq" = "IRQ_EDGE_LOW(GPP_C8_IRQ)" + device spi 0 on end + end + end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard |