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authorDuncan Laurie <dlaurie@chromium.org>2017-04-13 01:40:53 -0700
committerDuncan Laurie <dlaurie@chromium.org>2017-04-14 04:21:37 +0200
commite49b866c7cd67202853cd6e2177a294b9ab0c056 (patch)
tree164f12761d23c7f431e931545c26a6bb6acfd18d /src/mainboard/google/eve/chromeos.c
parent30783d84cffcb5a997e8d0f4061e3a7962b6417c (diff)
mainboard/google/eve: Set UART0 to skip initialization in FSP
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not set back to native mode by FSP when configured as GPIO input by coreboot. Now that FSP is not touching the pins I also removed the workaround to reconfigure the pins after FSP. BUG=b:35647877 BRANCH=none TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS is booted and they are not set back to native function by FSP. Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19264 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/eve/chromeos.c')
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