diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2016-06-02 17:58:18 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-21 13:59:55 +0200 |
| commit | 1ba34323010f075e21ed11d9cf2c97e688441676 (patch) | |
| tree | 12d98710a605745690c58f4adf3635fef5e6bcf0 /src/mainboard/google/enguarde/chromeos.fmd | |
| parent | 776498ac7ec537bab2a65101fd9640c1a7679f51 (diff) | |
google/enguarde: Upstream Lenovo N21 Chromebook
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-enguarde-5216.201.B
commit cf1f57b [Enguarde: Adjust rx delay for norm.]
TEST=built and booted Linux on enguarde with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15444
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/enguarde/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/enguarde/chromeos.fmd | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/enguarde/chromeos.fmd b/src/mainboard/google/enguarde/chromeos.fmd new file mode 100644 index 0000000000..113fba6e6f --- /dev/null +++ b/src/mainboard/google/enguarde/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + RW_SECTION_A@0x0 0xf0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0xdffc0 + RW_FWID_A@0xeffc0 0x40 + } + RW_SECTION_B@0xf0000 0xf0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0xdffc0 + RW_FWID_B@0xeffc0 0x40 + } + RW_MRC_CACHE@0x1e0000 0x10000 + RW_ELOG@0x1f0000 0x4000 + RW_SHARED@0x1f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x1f8000 0x2000 + RW_UNUSED@0x1fa000 0x6000 + RW_LEGACY(CBFS)@0x200000 0x200000 + WP_RO@0x400000 0x200000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x1f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x100000 + } + } + } +} |