diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-08-31 10:57:18 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-09-01 04:58:51 +0000 |
| commit | b1ae6ca7ef8b848e53577cb9da46c19d2d5886a8 (patch) | |
| tree | 8900b50b15d8934d7a1d8efc711ca8e7498ffe0d /src/mainboard/google/drallion | |
| parent | f3d54feef4c700991dd11b012f810162c5b6b06a (diff) | |
tree: Use boolean for s0ix_enable
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/drallion')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 302a09efe0..7238a064b4 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -39,7 +39,7 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 25, |