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authorMichael Niewöhner <foss@mniewoehner.de>2020-12-21 17:09:08 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-01-15 11:26:20 +0000
commitec1c0f53374effbab967cdb373f92e04a05e4443 (patch)
treecc65801f62c62ce8bee50d7194bbb55564b72165 /src/mainboard/google/drallion
parent7519ca42b53201083ec763058dadd8fdb2050f80 (diff)
mb/siemens/mc_apl1: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms. Early gpio configuration was done in romstage, while LPC pads were configured in bootblock. Instead of adding another dedicated gpio table for bootblock, move early gpio configuration completely to bootblock on these boards. This won't hurt, since there is no code touching the pads in between. The soc code gets dropped in CB:49410. Change-Id: I2a614afb305036b0581eac8ed6a723a3f80747b3 Tested-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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