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authorSubrata Banik <subratabanik@google.com>2022-01-03 18:29:05 +0000
committerFelix Held <felix-coreboot@felixheld.de>2022-01-17 15:49:24 +0000
commit805956bce30090ea8c047f3a5c102f38c47388ee (patch)
tree63b0fc35b6859c79da3f3c6fe5cc917907db774f /src/mainboard/google/drallion/variants
parent53c7453ba1ecdcd8c862cc535be2ae4082a17bdd (diff)
soc/intel/cnl: Use Kconfig to disable HECI1
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake and ensures disable_heci1() is guarded against this config. Also, makes dt CSE PCI device `on` by default. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google/drallion/variants')
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 105eddbb1f..fd1153c30e 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -411,7 +411,7 @@ chip soc/intel/cannonlake
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection