mb/google/drallion: Add memory init setup for drallion

This implementation adds below support
1. Add support to read memory strap
2. Add support to configure below memory parameters
  -> rcomp resistor configuration
  -> dqs mapping
  -> ect and ca vref config

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>

1 files changed, 8 insertions, 1 deletions

diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index c9f009e599..03bc17f185 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -58,11 +58,18 @@ static const struct cnl_mb_cfg memcfg = {
 	.vref_ca_config = 2,
 };
 
+const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
+{
+	return &memcfg;
+}
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	struct cnl_mb_cfg board_memcfg;
+
 	variant_mainboard_post_init_params(memupd);
 
 	wilco_ec_romstage_init();
 
-	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+	cannonlake_memcfg_init(&memupd->FspmConfig, get_variant_memory_cfg(&board_memcfg));
 }