mb/google/drallion: Add new mainboard

Drallion is a new mainboard using Intel Comet Lake SOC. As a starting
point, I took mainboard/sarien as the reference code and modified WHL
to Comet Lake.

BUG=b:138098572
Test=compiles

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 89 insertions, 0 deletions

diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c
new file mode 100644
index 0000000000..b3bf10296a
--- /dev/null
+++ b/src/mainboard/google/drallion/ramstage.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <boardid.h>
+#include <drivers/vpd/vpd.h>
+#include <smbios.h>
+#include <soc/gpio.h>
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#define VPD_KEY_SYSTEM_SERIAL		"serial_number"
+#define VPD_KEY_MAINBOARD_SERIAL	"mlb_serial_number"
+#define VPD_SERIAL_LEN			64
+
+const char *smbios_system_serial_number(void)
+{
+	static char serial[VPD_SERIAL_LEN];
+	if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO))
+		return serial;
+	return "";
+}
+
+const char *smbios_mainboard_serial_number(void)
+{
+	static char serial[VPD_SERIAL_LEN];
+	if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO))
+		return serial;
+	return "";
+}
+
+/* mainboard silk screen shows DIMM-A and DIMM-B */
+void smbios_fill_dimm_locator(const struct dimm_info *dimm,
+	struct smbios_type17 *t)
+{
+	switch (dimm->channel_num) {
+	case 0:
+		t->device_locator = smbios_add_string(t->eos, "DIMM-A");
+		break;
+	case 1:
+		t->device_locator = smbios_add_string(t->eos, "DIMM-B");
+		break;
+	default:
+		t->device_locator = smbios_add_string(t->eos, "UNKNOWN");
+		break;
+	}
+}
+
+static const struct pad_config gpio_unused[] = {
+/* SUSWARN# */		PAD_NC(GPP_A13, NONE),
+/* SUSACK# */		PAD_NC(GPP_A15, NONE),
+/* M2_SKT2_CFG0 */	PAD_NC(GPP_H12, NONE),
+/* M2_SKT2_CFG1 */	PAD_NC(GPP_H13, NONE),
+};
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	const struct pad_config *gpio_table;
+	size_t num_gpios;
+
+	gpio_table = variant_gpio_table(&num_gpios);
+	cnl_configure_pads(gpio_table, num_gpios);
+
+	/* Disable unused pads for devices with board ID > 2 */
+	if (board_id() > 2)
+		gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};