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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-24 01:23:28 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-28 12:57:51 +0000 |
| commit | ddd44f4fe9f45dfcdb2467073b4faf1fdb03ce47 (patch) | |
| tree | b29f7c11360e2d85945960277da46181c83c01fc /src/mainboard/google/drallion/ec.c | |
| parent | 84fde762e7c4e1a8e43194a9444b10b681e1cb50 (diff) | |
mb/supermicro/x11-lga1151-series: restructure and clean up devicetree
Drop zero-value devicetree options and move PcieRpEnable options down to
the corresponding devices.
Test: built with TIMELESS=1; binaries remain identical
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9285d786e973621a732e2627c734adc930e54207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/google/drallion/ec.c')
0 files changed, 0 insertions, 0 deletions