diff options
| author | Thejaswani Putta <thejaswani.putta@intel.com> | 2019-07-18 16:23:20 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-05 22:43:52 +0000 |
| commit | e3443d87ccaa3a845b595d3f056317f549ccdf6b (patch) | |
| tree | b091258d3a26144fb3603370ee687800d4ffda17 /src/mainboard/google/drallion/dsdt.asl | |
| parent | efe7947ac2ed0cbd827571bdcc10b5d891bad59e (diff) | |
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting
point, I took mainboard/sarien as the reference code and modified WHL
to Comet Lake.
BUG=b:138098572
Test=compiles
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/drallion/dsdt.asl | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl new file mode 100644 index 0000000000..2568800f91 --- /dev/null +++ b/src/mainboard/google/drallion/dsdt.asl @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/ec.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/cannonlake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + /* VPD support */ + #include <vendorcode/google/chromeos/acpi/vpd.asl> + /* MAC address passthru */ + #include <vendorcode/google/chromeos/acpi/amac.asl> +#endif + + /* Chipset specific sleep states */ + #include <soc/intel/cannonlake/acpi/sleepstates.asl> + + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/wilco/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/wilco/acpi/ec.asl> + } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } +} |