diff options
| author | Thejaswani Putta <thejaswani.putta@intel.com> | 2019-07-18 16:23:20 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-05 22:43:52 +0000 |
| commit | e3443d87ccaa3a845b595d3f056317f549ccdf6b (patch) | |
| tree | b091258d3a26144fb3603370ee687800d4ffda17 /src/mainboard/google/drallion/chromeos.fmd | |
| parent | efe7947ac2ed0cbd827571bdcc10b5d891bad59e (diff) | |
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting
point, I took mainboard/sarien as the reference code and modified WHL
to Comet Lake.
BUG=b:138098572
Test=compiles
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/drallion/chromeos.fmd | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd new file mode 100644 index 0000000000..ece0eda099 --- /dev/null +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_GBE(PRESERVE)@0x101000 0x2000 + SI_ME@0x103000 0x2f9000 + SI_PDR(PRESERVE)@0x3fc000 0x4000 + } + SI_BIOS@0x400000 0x1c00000 { + RW_DIAG@0x0 0x12d0000 { + RW_LEGACY(CBFS)@0x0 0x12c0000 + DIAG_NVRAM@0x12c0000 0x10000 + } + RW_SECTION_A@0x12d0000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x1550000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x17d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + WP_RO@0x1800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} |