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authorThejaswani Putta <thejaswani.putta@intel.com>2019-07-18 16:23:20 -0700
committerMartin Roth <martinroth@google.com>2019-08-05 22:43:52 +0000
commite3443d87ccaa3a845b595d3f056317f549ccdf6b (patch)
treeb091258d3a26144fb3603370ee687800d4ffda17 /src/mainboard/google/drallion/Makefile.inc
parentefe7947ac2ed0cbd827571bdcc10b5d891bad59e (diff)
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake. BUG=b:138098572 Test=compiles Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion/Makefile.inc')
-rw-r--r--src/mainboard/google/drallion/Makefile.inc38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc
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index 0000000000..c16e7d203d
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+++ b/src/mainboard/google/drallion/Makefile.inc
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+##
+## This file is part of the coreboot project.
+##
+## Copyright 2018 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += bootblock.c
+
+ramstage-y += ramstage.c
+ramstage-y += sku.c
+
+romstage-y += romstage.c
+
+smm-y += smihandler.c
+
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+
+bootblock-y += ec.c
+ramstage-y += ec.c
+romstage-y += ec.c
+verstage-y += ec.c
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include