mb/google/drallion: Add new mainboard

Drallion is a new mainboard using Intel Comet Lake SOC. As a starting
point, I took mainboard/sarien as the reference code and modified WHL
to Comet Lake.

BUG=b:138098572
Test=compiles

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 106 insertions, 0 deletions

diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
new file mode 100644
index 0000000000..deeca1503f
--- /dev/null
+++ b/src/mainboard/google/drallion/Kconfig
@@ -0,0 +1,106 @@
+
+config BOARD_GOOGLE_BASEBOARD_DRALLION
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_ISH
+	select DRIVERS_SPI_ACPI
+	select DRIVERS_USB_ACPI
+	select EC_GOOGLE_WILCO
+	select GENERIC_SPD_BIN
+	select GOOGLE_SMBIOS_MAINBOARD_VERSION
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_I2C_TPM_CR50
+	select MAINBOARD_HAS_TPM2
+	select SOC_INTEL_COMETLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM2
+	select MAINBOARD_USES_IFD_EC_REGION
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select USE_SAR
+	select SAR_ENABLE
+
+if BOARD_GOOGLE_BASEBOARD_DRALLION
+
+config CHROMEOS
+	bool
+	default y
+	select GBB_FLAG_FORCE_DEV_SWITCH_ON
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x4
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 82  # GPE0_DW2_18 (GPP_D18)
+
+config POWER_OFF_ON_CR50_UPDATE
+	bool
+	default n
+
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "DRALLION TEST 3556"
+
+config MAINBOARD_DIR
+	string
+	default "google/drallion"
+
+config MAINBOARD_FAMILY
+	string
+	default "Google_Drallion"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Drallion"
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config MAX_CPUS
+	int
+	default 8
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config VARIANT_DIR
+	string
+	default "drallion"
+
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config VBOOT
+	select HAS_RECOVERY_MRC_CACHE
+	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+	select VBOOT_LID_SWITCH
+
+endif # BOARD_GOOGLE_BASEBOARD_DRALLION