diff options
author | Aaron Durbin <adurbin@chromium.org> | 2020-05-27 08:31:26 -0600 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2020-05-28 19:38:33 +0000 |
commit | 0013623b7c976b8f79778cecf3f146dc7aeab6e9 (patch) | |
tree | 9cd19358a84a2ffe1c103f8186def1097be6d959 /src/mainboard/google/dragonegg/variants/baseboard/memory.c | |
parent | a85febcb1cfd31bd4d27e955fc2bcf9f8ef16cd5 (diff) |
mb/google/dragonegg: remove abandoned project
Dragonegg is no longer in development nor used. Remove it.
Change-Id: Ida30dba662bc517671824f8b70b73b4856836e97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dragonegg/variants/baseboard/memory.c')
-rw-r--r-- | src/mainboard/google/dragonegg/variants/baseboard/memory.c | 57 |
1 files changed, 0 insertions, 57 deletions
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/memory.c b/src/mainboard/google/dragonegg/variants/baseboard/memory.c deleted file mode 100644 index adb9ba63fe..0000000000 --- a/src/mainboard/google/dragonegg/variants/baseboard/memory.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/cpu.h> -#include <baseboard/variants.h> -#include <gpio.h> -#include <intelblocks/mp_init.h> -#include <variant/gpio.h> - -/* DQ byte map */ -static const u8 dq_map[][12] = { - { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } -}; - -/* DQS CPU<>DRAM map */ -static const u8 dqs_map[][8] = { - { 0, 1, 2, 3, 4, 5, 6, 7 }, - { 0, 1, 2, 3, 5, 4, 7, 6 }, -}; - -/* Rcomp resistor */ -static const u16 rcomp_resistor[] = { 100, 100, 100 }; - -void __weak variant_memory_params(struct lpddr4_config *mem_config) -{ - /* Rcomp target */ - static const u16 rcomp_target_es0[] = { 80, 40, 40, 40, 30 }; - static const u16 rcomp_target_es1[] = { 60, 20, 20, 20, 20 }; - - mem_config->dq_map = dq_map; - mem_config->dq_map_size = sizeof(dq_map); - mem_config->dqs_map = dqs_map; - mem_config->dqs_map_size = sizeof(dqs_map); - mem_config->rcomp_resistor = rcomp_resistor; - mem_config->rcomp_resistor_size = sizeof(rcomp_resistor); - if (cpu_get_cpuid() == CPUID_ICELAKE_A0) { - mem_config->rcomp_target = rcomp_target_es0; - mem_config->rcomp_target_size = sizeof(rcomp_target_es0); - } else { - mem_config->rcomp_target = rcomp_target_es1; - mem_config->rcomp_target_size = sizeof(rcomp_target_es1); - } -} - -int __weak variant_memory_sku(void) -{ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} |