diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2018-07-11 12:07:51 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-27 09:00:49 +0000 |
commit | 3a14338625d6ae7c6c4e8ee0b1e9be285593b3a6 (patch) | |
tree | 75e78040495541302dbc483bd87a36d51981b8d3 /src/mainboard/google/dragonegg/spd/Makefile.inc | |
parent | 13415333fedada138515a986afab799ca05a785f (diff) |
mb/google/dragonegg: Add initial mainboard code support
This patch includes support for both ICL ES0 and ES1 samples.
Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md
TEST=Able to build and boot dragonegg.
Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/dragonegg/spd/Makefile.inc')
-rw-r--r-- | src/mainboard/google/dragonegg/spd/Makefile.inc | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/mainboard/google/dragonegg/spd/Makefile.inc b/src/mainboard/google/dragonegg/spd/Makefile.inc new file mode 100644 index 0000000000..7aa9505e9e --- /dev/null +++ b/src/mainboard/google/dragonegg/spd/Makefile.inc @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_2GB # 0b000 +SPD_SOURCES += Hynix_H9HCNNNCPMMLHR_4GB # 0b001 +SPD_SOURCES += Micron_MT53E512M32D2NP_2GB # 0b010 +SPD_SOURCES += Micron_MT53E2G32D8QD_8GB # 0b011 + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd |