diff options
| author | Varun Joshi <varun.joshi@intel.corp-partner.google.com> | 2020-03-31 18:02:33 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2020-04-13 20:28:18 +0000 |
| commit | 2255ebaa23d5741e9f6179bfe8b6b3850b143ce8 (patch) | |
| tree | 80f073e455660ada08c04e0089f4ff6a2f30c5e9 /src/mainboard/google/deltaur/variants | |
| parent | c6f5b05cf383bd66c1f9e168394c7c0d86080a60 (diff) | |
mb/google/deltaur: Add support to enable GbE on variant
- Configure devicetree for enabling GbE on variant
and remove from baseboard.
- Configure Kconfig to enable GbE region.
- Configure fmd to incorporate GbE.
BUG=b:151102809
Cq-Depend: chrome-internal:2843183
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I1c36b132546049e3e775585c41164072f4ece73e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/google/deltaur/variants')
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 7 | ||||
| -rw-r--r-- | src/mainboard/google/deltaur/variants/deltan/overridetree.cb | 6 |
2 files changed, 7 insertions, 6 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index a63d66c834..a30c12d633 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -59,11 +59,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[4]" = "6" register "PcieClkSrcClkReq[4]" = "4" - # PCIe port root 8 (LAN), clock 3 - register "PcieRpEnable[7]" = "1" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" - register "PcieClkSrcClkReq[3]" = "3" - # PCIe root port 9 (NVMe), clock 2 register "PcieRpEnable[8]" = "1" register "PcieClkSrcUsage[2]" = "8" @@ -332,7 +327,7 @@ chip soc/intel/tigerlake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI Flash Controller - device pci 1f.6 on end # GbE Controller + device pci 1f.6 off end # GbE Controller device pci 1f.7 off end # Intel Trace Hub end end diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb index 32204c58e7..6a2719b960 100644 --- a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb +++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb @@ -1,6 +1,12 @@ chip soc/intel/tigerlake + # PCIe Port 8 for LAN + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" + register "PcieClkSrcClkReq[3]" = "3" + device domain 0 on + device pci 1f.6 on end # GbE 0x15FC end end |