diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-03-19 12:19:38 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-30 08:43:32 +0000 |
| commit | d8bff383c2c1ed40a03d664db25020197b67017c (patch) | |
| tree | dcdc1ea4f7043076244e257f872a640da246c4bb /src/mainboard/google/deltaur/variants/baseboard/include | |
| parent | 3a1a037231ddb5cdc03d0e147c2335de0f1c8ad6 (diff) | |
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of
the board.
BUG=b:150165131
BRANCH=none
TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/deltaur/variants/baseboard/include')
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index 8411900243..e6092b6123 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -4,10 +4,33 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H +#include <soc/gpe.h> #include <soc/gpio.h> +/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_C22 -#endif /* BASEBOARD_GPIO_H */ +/* Recovery mode */ +#define GPIO_REC_MODE GPP_A23 + +/* DDR channel enable pin */ +#define DDR_CHA_EN GPP_H4 +#define DDR_CHB_EN GPP_H5 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F11 +#define GPIO_MEM_CONFIG_1 GPP_F12 +#define GPIO_MEM_CONFIG_2 GPP_F13 +#define GPIO_MEM_CONFIG_3 GPP_F14 +#define GPIO_MEM_CONFIG_4 GPP_F15 + + +const struct pad_config *override_gpio_table(size_t *num); +const struct pad_config *override_early_gpio_table(size_t *num); +struct cros_gpio; +const struct cros_gpio *override_cros_gpios(size_t *num); + +#endif |