diff options
| author | Frank Wu <frank_wu@compal.corp-partner.google.com> | 2021-08-23 17:56:25 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-30 04:09:11 +0000 |
| commit | 91472fe5356c7756674a79ec7fcc608b41a8b587 (patch) | |
| tree | 46b9936c61b65b0c40837b7c1fc8c0b58622f189 /src/mainboard/google/dedede | |
| parent | f04a912818f058dd77782d25e78e0c2a96aedc04 (diff) | |
mb/google/dedede/var/driblee: Configure thermal sensor setting
According to schematics, TSR2 thermal sensor is not present in driblee.
BUG=b:191732473, b:197180925, b:195868075
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I343a6161f71f66b77d23f1fa2f581aaee5eddf1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57091
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede')
| -rw-r--r-- | src/mainboard/google/dedede/variants/driblee/overridetree.cb | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb index 4b0987f1aa..083e515719 100644 --- a/src/mainboard/google/dedede/variants/driblee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb @@ -41,6 +41,42 @@ chip soc/intel/jasperlake register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN) + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on |