diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2021-03-31 14:35:26 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2021-04-05 14:31:08 +0000 |
| commit | 7164ad74bf1f2006b85670e9e74aefdf643173a8 (patch) | |
| tree | 42a47da3020cde9152b2605bec822f046592b878 /src/mainboard/google/dedede/variants | |
| parent | f7f715dff38c4a629139b2493ed6e0d7cc2eb36f (diff) | |
mb/google/dedede: add discrete TPM 2.0 configuration
There are forthcoming designs that will be utilizing
a discrete TPM 2.0 solution. Split the existing dedede
configuration options so future mainboard variants can
easily select the appropriate Kconfig option using the
newly introduced options:
- BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
- BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
The existing variants all select the former option,
BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 since all those
designs currently utilize Cr50.
BUG=b:184151664
Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/gpio.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index c162ac3780..79bae96476 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -72,6 +72,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR/GSPI0_CS1_N */ PAD_NC(GPP_B14, NONE), +#if CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50) /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -80,6 +81,13 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), +#else /* BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 */ + /* Nothing connected on GSPI1 */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), +#endif /* B19 : GSPI1_CS0_N */ PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK */ @@ -389,6 +397,7 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), +#if CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50) /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -397,6 +406,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), +#endif /* C0 : RAM_STRAP_0 */ PAD_CFG_GPI(GPP_C0, NONE, DEEP), |