diff options
| author | Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> | 2021-01-18 21:05:47 +0800 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2021-01-21 05:08:54 +0000 |
| commit | 68d19f83c39ff758a78883a4fa98e59ff330eb59 (patch) | |
| tree | 491cf61149006e6b2d98f98adc20de8532b709ae /src/mainboard/google/dedede/variants | |
| parent | 34e84b5858484a12d8397fb54551455e59f22b79 (diff) | |
mb/google/dedede/var/boten: Update gpio setting
Correct GPIO settings as below reason:
1. GPP_D19/GPP_D20/GPP_D21 not being used but set to NF.
2. GPP_B7 should configure as WWAN SAR detect ODL, but set to NC
BUG=b:175932166
BRANCH=dedede
TEST=emerge-dedede coreboot chromeos-bootimage and boot into emmc
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id7780d5332551ed3fd20ef14f8b5d31164f16385
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants')
| -rw-r--r-- | src/mainboard/google/dedede/variants/boten/gpio.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index eb5e3c3cc8..2ac76aff6e 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -10,6 +10,9 @@ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), + /* B7 : WWAN_SAR_DETECT_R_ODL */ + PAD_CFG_GPO(GPP_B7, 1, DEEP), + /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), /* C18 : AP_I2C_EMR_SDA */ @@ -25,6 +28,12 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D14, NONE), /* D15 : UCAM_RST_L */ PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), /* D22 : AP_I2C_SUB_SDA*/ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* D23 : AP_I2C_SUB_SCL */ |