diff options
| author | Ben Kao <ben.kao@intel.com> | 2021-07-04 21:24:36 +0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-07-26 05:00:51 +0000 |
| commit | 6eb52534513beda06e7787ee550c02198a447d5c (patch) | |
| tree | 7c3eed5fc4fec5f853354de506152e1ec074fecc /src/mainboard/google/dedede/variants | |
| parent | 3b28ab098ec1e7f1ffadb335f110b584a82e83f5 (diff) | |
soc/intel/jasperlake: Set xHCI LFPS period sampling off time
Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.
The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.
BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 9064297c74..cb5321c773 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -206,6 +206,9 @@ chip soc/intel/jasperlake # Enable HECI register "HeciEnabled" = "1" + # Set xHCI LFPS period sampling off time, the default is 9ms. + register "xhci_lfps_sampling_offtime_ms" = "9" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |